In miniaturizing certain semiconductor devices, pre-processing may be required to form a silicide layer. In miniaturized semiconductor devices, shallow diffusion regions are formed, and the size of the gate electrode, formed of silicon, is reduced. To form the shallow diffusion regions and to form a gate electrode having a lower resistance, a self-aligned silicide layer is proposed. The silicide layer is formed to the shape of a silicon region.
In salicide technology, a metal, such as cobalt, is first deposited on a silicon substrate having an insulating region formed therein. Next, the silicon substrate is annealed to form a silicide layer through a silicide reaction between the silicon and the metal. The silicide layer is selectively formed by removing the metal which has not yet reacted.
In order to form a good silicide layer, the surface of the silicon substrate should be rinsed to remove a native oxide film. Rinsing should occur before forming the metal film. If the native oxide film is not removed, it will interfere with a diffusion process that occurs between the silicon and metal. In this case, insufficient silicide reaction occurs and thereby a silicide layer having lower resistance cannot be formed.
The above described salicide technology is described, for example, in Japanese Published Unexamined Patent application No. 2002-334850 (Published on Nov. 22, 2002) Corresponding U.S. Pat. No. 6,475,893 B2 (Published on Nov. 5, 2002).
However, with still further miniaturization of semiconductor devices, fluctuations in the uniformity of the silicide layer and fluctuations in silicide resistance are problems that occur even if one or more of the known cleaning processes is performed. Accordingly, a better cleaning method is required for the smaller devices.